The present invention relates in general to the protection of integrated circuits (IC) and, more particularly, to a substrate injection clamp for preventing undesirable current injection into the P-substrate thereof.
The need for protecting the parasitic diode, formed between adjacent N-epitaxial (N-epi) and P-substrate regions, is well known and applicable to most if not all bipolar technologies. If a negative voltage is applied to the N-epi region, the parasitic diode could become forward biased injecting current into the P-substrate which could seriously degrade the performance of, or even destroy the IC.
One protection technique uses a separate clamping circuit coupled to the vulnerable N-epi region for limiting the voltage applied thereto. This technique is satisfactory for low current applications; however, the clamping circuit would require an unacceptably large die area to realize high current protection, e.g. above a few milliamps (mA).
Another technique, commonly known as a moat, increases the base channel spacing between the collector and emitter of the parasitic NPN transistor formed between two N-epi regions and the P-substrate thereby lowering the forward current transfer ratio thereof, typically to less than 0.001, and increasing the minimum current required for conduction through the parasitic diode. The moat technique imposes undesirable restrictions upon the geometric placement of the N-epi regions to ensure the low forward current transfer ratio.
Hence, there is a need for a high current substrate injection clamp requiring minimal die area and imposing no undue restrictions in the geometric layout of the IC.